Since the disclosure of integrated circuits by Dr. Jack Kilby of Texas Instruments in early years, scientists and engineers have made numerous disclosures and improvements in semiconductor devices and processes. Over 50 years, the dimension of semiconductors have been significantly reduced, which translates into an increasing processing speed and decreasing power consumption. To date, the development of semiconductors has largely followed Moore's Law, which roughly states that the number of transistors in dense integrated circuits doubles about every two years. At present, semiconductor processes are developing toward below 20 nm, and some companies are embarking on 14 nm processes. Just to provide a reference herein, a silicon atom is about 0.2 nm, which means that the distance between two separate components manufactured by a 20 nm process is about only one hundred silicon atoms.
Semiconductor device manufacturing has therefore become increasingly challenging and advancing toward the physically possible limit. One of recent developments in semiconductor technologies has been the use of silicon germanium (SiGe) in semiconductor manufacturing. With the evolution of integrated circuit developments, the functional densities (for example, the number of interconnects per chip region) are also generally increasing as geometries (that is, the smallest elements or lines that can be produced using a process) are reduced. This downsizing process can often offer benefits by increasing productivity and lowering related costs. However, it is challenging how to design a reasonable transistor structure to reduce its volume.
Currently in integrated circuits, a smallest memory cell typically includes a memory transistor and a select transistor matching with the memory transistor, and the memory transistor portion has an SONOS (Silicon (gate)-Oxide-Nitride-Oxide-Silicon (substrate)) structure, and the select transistor portion is a conventional MOS tube. In the prior art, as shown in FIG. 1, a conventional smallest memory cell generally consists of a conventional nMOS transistor (select transistor) formed on a P-type well and an SONOS memory transistor formed on a memory well respectively, and includes an N-type semiconductor substrate 101, a select transistor P-type well 102, a memory transistor P-type well 103, a select gate 105 isolated from the select transistor well 102 by an oxide layer 104, and a memory gate 107 isolated from the memory transistor well 103 by an ONO layer 106.
As can be seen from FIG. 1, there is a large gap between the select gate 105 and the memory gate 107 in the conventional transistor with the SONOS structure. As semiconductor processes have become increasingly demanding on critical dimensions (CDs), the volume of elements is expected to decrease correspondingly. Therefore, there is an urgent need for a reasonable and simple manufacturing process to manufacture a small-dimension transistor with an SONOS structure, so that the small-dimension transistor with an SONOS structure can adapt to different work requirements as a smallest memory cell.